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vishay siliconix si9122e document number: 73866 s-80112-rev. d, 21-jan-08 www.vishay.com 1 500-khz half-bridge dc/dc controller with integrated secondary sync hronous rectification drivers description si9122e is a half-bridge controller ic ideally suited to fixed telecom applications where high efficiency is required at low output voltages (e.g. < 3.3 v). designed to operate within the fixed telecom voltage range of 36 v to 75 v, the ic is capable of controlling and driving both the low and high-side switching devices of a half bridge circuit and also controlling the switching devices on the second ary side of the bridge. due to the very low on-resistance of the secondary mosfets, a significant increase in conversion efficiency can be achieved as compared with conventional schottky diodes. control of the secondary devices is by means of a pulse transformer and a pair of inverters. such a system has efficiencies well in excess of 90 % even for low output voltages. on-chip control of the dead ti me delays between the primary and secondary synchronous signals keep efficiencies high and prevent shorting of the power transformer. an external resistor sets the oscillator frequency from 200 khz to 500 khz. si9122e has advanced current monitoring and control circuitry which allow the user to set the maximum current in the primary circuit. such a feature acts as protection against output shorting and also provides constant current into large capacitive loads during start-up or when paralleling power supplies. current sensing is by means of a sense resistor on the low-side primary device. features ? 92 % primary/secondary duty cycle ? 135 c over temperature protection ? compatible with etsi 300 132-2 ? 28 v to 75 v input voltage range ? integrated 1 a half bridge primary drivers ? secondary synchronous rectifier control signals with programmable deadtime delay ? voltage mode control ? voltage feedforward compensation ? high voltage pre-regulator operates during start-up ? current sensing on low-side primary device ? frequency foldback eliminates constant current tail ? advanced maximum current control during start-up and shorted load ? low input voltage detection ? programmable soft-start function applications ? network cards ? power supply modules ? distributed power systems ? intermediate bus converter ? brick converter functional block diagram and pin configuration figure 1. bst dh lx dl cs2 cs1 ep c l_co n t p m o c _ g e r v n i v c c v i n det s s v f e r r c s o m b b d n g d n g p si9122e 36 v to 75 v synchrono u s rectifiers v cc - + v ref error amplifier opto isolator v out + - 1 v to 12 v typ. sr h sr l rohs compliant
www.vishay.com 2 document number: 73866 s-80112-rev. d, 21-jan-08 vishay siliconix si9122e technical description si9122e is a voltage mode controller for the half-bridge topology. with 100 v depletion mode mosfet, the si9122e is capable of powering directly from the high voltage bus to v cc through an external pnp pass transistor, or may be powered through an external regulator directly through the v cc pin. with pwm control, si9122e provides peak efficiency throughout the entire line and load range. in order to simplify the design of efficient secondary synchronous rectification circuitry, the si 9122e provides intelligent gate drive signals to control the secondary mosfets. with independent gate drive signals from the controller, transformer design is no longer limited by the gate to source rating of the secondary-side mosfets. si9122e provides constant v gs voltage, independent of the line voltage to minimize the gate charge loss as well as conduction loss. to prevent shoot-through current or transformer shorting, adjustable break-before-make (bbm) time is incorporated into the ic and is programmed by an external precision resistor. si9122e is assembled in lead (pb)-free tssop-20 and mlp65-20 packages. to satisfy stringent ambient temperature requirements, si9122e is rated to handle the industrial temperature range of - 40 c to 85 c. when a situation arises which results in a rapid increase in primary (or secondary) current such as output shorted or start-up with a large output capacitor, control of the pwm generator is handed over to the current loop. monitoring of the load current is by means of an external current sense resistor in the source of the primary lo w-side switch. with the lower otp set at 135 c , the dnf20 package improves the thermal headroom. figure 2. v ref - + pre-reg u lator - + - + reg_comp v i n det v ref v i n + ? error amplifier 132 k ep ? + p w m comparator ss ? + cs2 cs1 o v er c u rrent protection g n d v u v lo v u v v sd v cc d u ty cycle control c l_co n t dri v er control and timing bbm otp osc r osc v ff ramp sr l sr h pg n d dl dh sy n c dri v er lo w sy n c dri v er high lo w -side dri v er high-side primary dri v er int bst lx si9122e peak det v ref 2 60 k i ss 8 . 8 v 550 m v 20 a 8 v 9.1 v v cc v cc v cc primary absolute maximum ratings all voltages referenced to gnd = 0 v parameter limit unit v in (continuous) 80 v v in (100 ms) 100 v cc 14.5 v bst continuous 95 100 ms 113.2 v lx 100 v bst - v lx 15 v ref , r osc - 0.3 to v cc + 0.3 logic inputs - 0.3 to v cc + 0.3 analog inputs - 0.3 to v cc + 0.3 hv pre-regulator input current continuous 5 ma
document number: 73866 s-80112-rev. d, 21-jan-08 www.vishay.com 3 vishay siliconix si9122e notes: a. device mounted on jedec compliant 1s2p test board. b. derate 14 mw/c above 25 c. c. derate 26 mw/c above 25 c. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indi cated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended per iods may affect device reliability. parameter limit unit storage temperature - 65 to 150 c operating junction temperature 150 power dissipation a tssop-20 b mlp65-20 c 850 2500 mw thermal impedance ( ja ) tssop-20 mlp65-20 75 38 c/w recommended operating range all voltages refere nced to gnd = 0 v parameter limit unit v in 36 to 75 v v cc 10.5 to 13.2 cv cc 4.7 f f osc 200 to 500 khz r osc 30 to 72 k r bbm 22 to 50 c ref 0.1 f c boost 0.1 analog inputs 0 to v cc - 2 v digital inputs 0 to v cc reference voltage output current 0.1 to 2.5 ma absolute maximum ratings all voltages referenced to gnd = 0 v specifications a parameter symbol test conditions unless otherwise specified f nom = 500 khz, v in = 75 v v indet = 7.5 v; 10.5 v v cc 13.2 v limits - 40 to 85 c unit min. b typ. c max. b reference (3.3 v) output voltage v ref v cc = 12 v, 25 c load = 0 ma 3.2 3.3 3.4 v short circuit current i sref v ref = 0 v - 50 ma load regulation dvr/dir i ref = 0 to - 2.5 ma - 30 - 75 mv power supply rejection psrr at 100 hz 60 db oscillator accuracy (1 % r osc ) r osc = 30 k , f nom = 500 khz - 20 20 % max frequency g f max r osc = 22.6 k 400 500 600 khz foldback frequency d f fobk f nom = 500 khz, v cs2 - v cs1 > 150 mv 100 error amplifier input bias current i bias v ep = 0 v - 40 - 15 a gain a v - 2.2 v/v bandwidth bw 5 mhz power supply rejection psrr at 110 hz 60 db slew state sr 0.5 v/ s
www.vishay.com 4 document number: 73866 s-80112-rev. d, 21-jan-08 vishay siliconix si9122e parameter symbol test conditions unless otherwise specified f nom = 500 khz, v in = 75 v v indet = 7.5 v; 10.5 v v cc 13.2 v limits - 40 to 85 c unit min. b typ. c max. b current sense amplifier input voltage cm range v cm v cs1 - gnd, v cs2 - gnd 150 mv current sense amplifier input amplifier gain a vol 17.5 db input amplifier bandwidth bw 5 mhz input amplifier offset voltage v os 5 mv c l_cont current i cl_cont dv cs = 0 120 a dv cs = 100 mv 0 dv cs = 100 mv > 2 ma lower current limit threshold v tlcl i pd = i pu - i cl_cont = 0 100 mv upper current limit threshold v thcl i pd > 2 ma 150 hysteresis i pu < 500 a - 50 c l_cont clamp level c l_cont i pu = 500 a 0.6 1.5 v pwm operation duty cycle d max f osc = 500 khz, 25 c v indet = 4.8 v, v in = 48 v v ep = 0 v primary 88 91 94 % secondary 90 93 95 % d min v ep = 1.75 v < 17 v cs2 - v cs1 > 150 mv 3 pre-regulator input voltage + v in i in = 10 a 36 75 v input leakage current i lkg v in = 75 v, v cc > v reg 10 a regulator bias current i reg1 v in = 75 v, v indet < v sd 86 200 i reg2 v in = 75 v, v indet > v ref 814ma regulator_comp i source v cc = 12 v - 29 - 19 - 9 a i sink 50 82 110 pre-regulator drive capability i start v cc < v reg 20 ma v cc pre-regulator turn off threshold voltage v reg1 v indet > v ref 7.4 9.1 10.4 v t a = 25 c 8.5 9.1 9.7 v reg2 v indet = 0 v 9.2 undervoltage lockout v uvlo v cc rising 7.15 8.8 9.8 t a = 25 c 8.1 8.8 9.3 v ulvo hysteresis f v uvlohys 0.5 soft-start soft-start current output i ss start-up condition 12 20 28 a soft-start completion voltage v ss_comp normal operation 7.35 8.05 8.85 v shutdown v indet shutdown v sd v indet rising 350 550 720 mv v sd hysteresis v indet falling 200 v indet input threshold protection v indet - v in under voltage v uv v indet rising 3.13 3.3 3.46 v v uv hysteresis v indet falling 0.23 0.3 0.35 over temperature voltages activating temperature otp_on t j increasing 135 c de-activating temperature otp_off t j decreasing 113 specifications a
document number: 73866 s-80112-rev. d, 21-jan-08 www.vishay.com 5 vishay siliconix si9122e notes: a. refer to process option flowchart for additional information. b. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum (- 40 c to 85 c). c. typical values are for design aid only, no t guaranteed nor subject to production testing. d. f min when v c l_cont at clamp level. typical foldback frequen cy change + 20 %, - 30 % over temperature. e. see figure 3 for break-bef ore-make time definition. f. v uvlo tracks v reg1 by a diode drop. g. guaranteed by design and characte rization, not tested in production. parameter symbol test conditions unless otherwise specified f nom = 500 khz, v in = 75 v v indet = 7.5 v; 10.5 v v cc 13.2 v limits - 40 to 85 c unit min. b typ. c max. b converter supply current (v cc ) shutdown i cc1 shutdown, v indet = 0 v 50 350 a converter supply current (v cc ) switching disabled i cc2 v indet < v ref 4812 ma switching w/o load i cc3 v indet > v ref, f nom = 500 khz 51015 switching with c load i cc4 v cc = 12 v, c dh = c dl = 3 nf c sr h = c sr l = 0.3 nf 21 output mosfet dh driver (high-side) output high voltage v oh sourcing 10 ma v bst - 0.3 v output low voltage v ol sinking 10 ma v lx + 0.3 boost current i bst v lx = 48 v, v bst = v lx + v cc 1.3 1.9 2.7 ma lx current i lx v lx = 48 v, v bst = v lx + v cc - 1.3 - 0.7 - 0.4 peak output source i source v cc = 10.5 v - 1.0 - 0.75 a peak output sink i sink 0.75 1.0 rise time t r c dh = 3 nf 35 ns fall time t f 35 output mosfet dl driver (low-side) output high voltage v oh sourcing 10 ma v cc - 0.3 v output low voltage v ol sinking 10 ma 0.3 peak output source i source v cc = 10.5 v - 1.0 - 0.75 a peak output sink i sink 0.75 1.0 rise time t r c dh = 3 nf 35 ns fall time t f 35 synchronous rectifier (sr h , sr l ) drivers output high voltage v oh sourcing 10 ma v cc - 0.4 v output low voltage v ol sinking 10 ma 0.4 break-before-make time e t bbm1 t a = 25 c, r bbm = 33 k , v indet = 4.8 v, v ep = 0 v, v in = 48 v 48 ns t bbm2 9 t bbm3 t a = 25 c, r bbm = 33 k , bst= 60 v, v indet = 4.8 v, v ep = 0 v, v in = 48 v = lx 24 t bbm4 18 peak output source i source v cc = 10.5 v - 100 ma peak output sink i sink 100 rise time t r c dh = 3 nf 35 ns fall time t f 35 voltag e mode error amplifier t d1dh input to high-side switch off < 200 ns t d2dl input to low-side switch off < 200 current mode current amplifier t d3dh input to high-side switch off < 200 ns t d4dl input to low-side switch off < 200 specifications a
www.vishay.com 6 document number: 73866 s-80112-rev. d, 21-jan-08 vishay siliconix si9122e timing diagram for mos drivers figure 3. g n d time v cc v bst v mid g n d v cc p w mp w mp w mp w m sr l sr l dl dl dh dh dh dh sr h sr h t bbm1 t bbm2 t bbm3 t bbm4 50 % dh lx 50 % t bbm3 t bbm4 dh , lx dh , lx dh , lx sr h sr l g n d g n d v cc v mid bst = lx + v cc t bbm1 t bbm2 v cc g n d sr l dl g n d g n d v cc v cc v lx
document number: 73866 s-80112-rev. d, 21-jan-08 www.vishay.com 7 vishay siliconix si9122e pin configuration 20 19 1 8 17 1 2 3 4 16 15 14 13 5 6 7 8 v i n bst reg_comp dh v cc lx v ref dl g n dpg n d r osc sr h ep sr l v i n det ss si9122edq (tssop-20) top v ie w 12 11 9 10 cs1 bbm cs2 c l_co n t si9122edlp (mlp65-20) top v ie w bst dh lx dl pg n d sr h sr l ss bbm c l_co n t v i n reg_comp v cc v ref g n d r osc ep v i n det cs1 cs2 20 19 1 8 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 ordering information part number temperature range package si9122edq-t1-e3 - 40 c to 85 c tssop-20 SI9122EDLP-T1-E3 mlp65-20 eval board temperature range board type contact factory - 10 c to 70 c surface mount and thru-hole pin description 1 v in input supply voltage for the start-up circuit 2 reg_comp control signal for an external pass transistor 3 v cc supply voltage for in ternal circuitry 4 v ref 3.3 v reference 5 gnd ground 6 r osc external resistor c onnection to oscillator 7 ep voltage control input 8 v indet v in under voltage detect and shutdown function input. shuts down or disables switching when v indet falls below preset threshold voltages and provides the feed forward voltage. 9 cs1 current limit amplifier negative input 10 cs2 current limit amplifier positive input 11 c l_cont current limit compensation 12 bbm programmable break-before-make time connecti on to an external resistor to set time delay 13 ss soft-start control - external capacitor connection 14 sr l signal transformer drive, sequenced with the primary side. 15 sr h signal transformer drive, sequenced with the primary side 16 pgnd power ground 17 dl low-side gate drive signal - primary 18 lx high-side source and transformer connection node 19 dh high-side gate drive signal - primary 20 bst bootstrap voltage to drive the high-side n-channel mosfet switch
www.vishay.com 8 document number: 73866 s-80112-rev. d, 21-jan-08 vishay siliconix si9122e detailed option start-up when v inext rises above 0 v, the internal pre-regulator begins to charge up the v cc capacitor. current into the external v cc capacitor is limited to typically 40 ma by the internal dmos device. when v cc exceeds the uvlo voltage of 8.8 v a soft-start cycle of the switch mode supply is initiated. the v cc supply continues to be charged by the pre-regulator until v cc equals v reg . during this period, between v uvlo and v reg , excessive load current will result in v cc falling below v uvlo and stopping switch mode operation. this situation is avoided by the hysteresis between v reg and v uvlo and correct sizing of the v cc capacitor, bootstrap capacitor a nd the soft-start capacitor. the value of the v cc capacitor should therefore be chosen to be capable of maintaining switch mode operation until the required v cc current can be supplied from the external circuit (e.g via a power transformer winding and zener regulator). feedback from the output of the switch mode supply charges v cc above v reg and fully disconnects the pre-regulator, isolating v cc from v in . v cc is then maintained above v reg for the duration of switch mode operation. in the event of an over voltage condition on v cc , an internal voltage clamp turns on at 14.5 v to shunt excessive current to gnd. care needs to be taken if there is a delay prior to the external circuit feeding back to the v cc supply. to prevent excessive power dissipation within the ic it is advisable to use an external pnp device. a pin has been incorporated on the ic, (reg_comp) to provide compensation when employing the external device. in this case the v in pin is connected to the base of the pnp device and controls the current, while the reg_comp pin determines t he frequency compensation of the circuit. the value of the reg_comp capacitor cannot be too big, otherwise it will slow down the response of the pre-regulator in the case that fault situations occur and pre-regulator needs to be turned on again. to understand the operation, please refer to figure 5. figure 4. detailed si9122e block diagram timer + ? 132 k ep + ? bandgap reference 3.3 v osc loop control 135 c temp protection high v oltage interface v sd v u v v u v lo logic clock otp v ref v i n det ? + r osc oscillator clock 60 k v ref /2 p w m generator ? + ? + v u v v sd v ref 550 m v logic dh bst lx high-side primary dri v er dl sr h sr l pg n d lo w -side primary dri v er synchrono u s dri v er (high) synchrono u s dri v er (lo w ) bbm c u rrent control gain 100 m v cs2 cs1 blanking c l_co n t v cc 20 a soft-start ss ena b le ss si9122e 8 v ? + ? + v reg 9.1 v v cc v i n pre-reg u lator v u v lo 8 . 8 v 9.1 v v cc v cc v cc g n d v oltage feedfor w ard fre qu ency fold b ack c l_co n t 12 v
document number: 73866 s-80112-rev. d, 21-jan-08 www.vishay.com 9 vishay siliconix si9122e the soft-start circuit is designed for the dc-dc converter to start-up in an orderly manner and reduce component stresses on the converter. th is feature is programmable by selecting an external c ss . an internal 20 a current source charges c ss from 0 v to the final clamped voltage of 8 v. in the event of uvlo or shutdown, v ss will be held low (< 1 v) disabling driver switching. to prevent oscillations, a longer soft-start time may be needed for highly capacitive loads and/or high peak output current applications. reference the reference voltage of si9122e is set at 3.3 v. the reference voltage should be de-coupled externally with 0.1 f capacitor. the v ref voltage is 0 v in shutdown mode and has 50 ma source capability. voltage mode pwm operation under normal load conditions, the ic operates in voltage mode and generates a fixed frequency pulse width modulated signal to the drivers. duty cycle is controlled over a wide range to maintain output voltage under line and load variation. voltage feedforward is also included to take account of variations in supply voltage v in . in the half-bridge topology requ iring isolation between output and input, the reference voltage and error amplifier must be supplied externally, usually on the secondary side. the error information is thus passed to the power controller through an opto-coupling device. this information is inverted, hence 0 v represents the maximum duty cycle, while 2 v represents minimum duty cycle. the error information enters the ic via pin ep, and is passed to the pwm generator via an inverting amplifier. the relationship between duty cycle and v ep is shown in the typical characteristic graph, duty cycle vs. v ep 25 c , page 12. voltage feedforward is implemented by taking the attenuated v in signal at v indet and directly modulating the duty cycle. at start-up, i.e., once v cc is greater than v uvlo , switching is initiated under soft-start c ontrol which increases primary switch on-times linearly from d min to d max over the soft-start period. start-up from a v indet power down is also initiated under soft-start control. half bridge and synchronous rectification timing sequence the pwm signal generated within the si9122e controls the low and high-side bridge driv ers on alternative cycles. a period of inactivity always results after initiation of the soft- start cycle until the soft-start voltage reaches approximately 1.2 v and pwm controlled switching begins. the first bridge driver to switch is always the low-side (dl), as this allows charging of the high-side boost capacitor. the timing and coordination of the drives to the primary and secondary stages is very important and shown in figure 3. it is essential to avoid the situation where both of the secondary mosfets are on when either the high or the low- side switch are active. in this situation the transformer would effectively be presented with a short across the output. to avoid this, a dedicated break-before-make circuit is included which will generate non-overlapping waveforms for the primary and the secondary drive signals. this is achieved by a programmable timer which delays the on switching of the primary driver relative to t he off switching of the related secondary and subsequently delays the on switching of the secondary relative to the off switching of the related primary. typical variations of bbm times with respect to r bbm and other operating parameters are shown on page 14 and 15. primary high- and low-side mosfet drivers the drive voltage for the lo w-side mosfet switch is provided directly from v cc . the high-side mosfet however requires the gate voltage to be enhanced above v in . this is achieved by bootstrapping the v cc voltage onto the lx voltage (the high-side mosfet source). in order to provide the bootstrapping an external diode and capacitor are required as shown on the application schematic. the capacitor will charge up after the low-side driver has turned on. the switch gatedrive signals dh and dl are shown in figure 3. secondary mosfet drivers the secondary side mosfets are driven from the si9122e via a center tapped pulse tran sformer and inverter drivers. the waveforms from sr h and sr l are shown in figure 3. of importance is the relative voltage between sr h and sr l , i.e. that which is presented ac ross the primary of the pulse transformer. when both potentials of sr l and sr h are equal then by the action of the in verting drivers both secondary mosfets are turned on. oscillator the oscillator is designed to operate at a nominal frequency of 500 khz. the 500 khz operating frequency allows the converter to minimize the inductor and capacitor size, improving the power density of the converter. the oscillator and therefore the switching frequency is programmable by attaching a resistor to the r osc pin. under overload conditions the oscillator frequency is reduced by the current overload protection to enable a constant current to be maintained into a low impedance circuit. current limit current mode control providing constant current operation is achieved by monitoring the differential voltage v cs between the cs1 and cs2 pins, which are connected to a current sense resistor on the primar y low-side mosfet. in the absence of an overcu rrent condition, v cs is less than lower current limit threshold v tlcl (typical 100 mv); c l_cont is pulled up linearly via the 120 a current source (i pu ) and both dl and dh switch at half the oscillator set frequency. when a moderate overcurrent condition occurs (v tlcl < v cs < v thcl ), the c l_cont capacitor will be discharged at a rate that is proportional to v cs - 100 mv by the i pd current source. both driver outputs are in frequency fold-back mode and the switching frequency becomes roughly 20 % of
www.vishay.com 10 document number: 73866 s-80112-rev. d, 21-jan-08 vishay siliconix si9122e normal switching frequency. when a severe overcurrent condition occurs (v thcl < v cs ), the nmos discharges c l_cont capacitor immediately at 2 ma rate and the c l_cont voltage will be clamped to 1.2 v disabling both dl and dh outputs. before v cs reaches severe overcurrent condition, a lowering of the c l_cont voltage results in pwm control of the output drive being taken over by the current limit control loop through c l_cont . current control initially reduces the switching duty cycle toward the minimum the chip can reach (d min ). if this duty cycle reducti on still cannot lower the load current, then the switching frequency will start to fold back to minimum 1/5 of the nominal frequency. this prevents the on-time of the primary drivers from being reduced to below 100 ns and avoids current tails. if v cs > v thcl , the switching will then stop. with constant current mode control and frequency foldback, protection of the mosfet s witches is increased. the converter reverts to voltage mode operation immediately when the primary current falls below the limit level, and c l_cont capacitor is charged up and clamped to 6.5 v. the soft-start function does not appl y during current limit period, as this would constitute hiccup mode operation. v in voltage monitor - v indet the chip provides a means of sensing the voltage of v in , and withholding operation of the output drivers until a minimum voltage of v ref (3.3 v, 300 mv hyster esis), is achieved. this is achieved by choosing an appropriate resistive tap between the ground and v in , and comparing this voltage with the reference voltage. when the applied voltage is greater than v ref , the output drivers are activated as normal. v indet also provides the input to the voltage feedforward function. however, if the divided voltage applied to the v indet pin is greater than v cc - 0.3 v, the high-side driver, dh, will stop switching until the voltage drops below v cc - 0.3 v. thus, the resistive tap on the v in divider must be set to accommodate the normal v cc operating voltage to avoid this condition. alternatively, a zener clamp diode from v indet to gnd may also be used. shutdown mode if v indet is forced below the lower v sd threshold, the device will enter shutdown mode. this powers down all unnecessary functions of the controller, ensures that the primary switches are off, and results in a low level current demand from the v in or v cc supplies. figure 5. high-voltage pre-regulator circuit c v cc 0.5 f c ext 2 nf g n d v cc p n p ext reg_comp v ref v i n v i n ext h v dmos 14.5 v r ext 12 v a u xillary v cc figure 6. current limit circuit - + gm c ext + - a v a v 150 m v - + gm peak detect blank cs1 cs2 i pd 0 to 240 a (nom) i pu 120 a (nom) a v v offset osc c l_clamp r ext c l_co n t a v 100 m v v cc
document number: 73866 s-80112-rev. d, 21-jan-08 www.vishay.com 11 vishay siliconix si9122e reduction of bbm 2, 4 at higher f osc the start of a switching period is defined as the turning point of the oscillator, marked in figu re 7 as a, with the end of a switching period marked as b. for a half bridge, two switching periods are required for both the primary high-side and low-side drivers to operate as shown in figure 3. for a given oscillator frequency there is a finite time in which all events from equation (1) have to occur. these are t dt dead- time duration which is a function of v ep , t pd1 is the propagation delay from the pwm to sr l (or sr h ) output going low, t bbm1 (or t bbm3 ) rise delay, dl (or dh) primary driver on-time, t pd2 is the propagation delay from pwm to dl (or dh) output going low and t bbm2 (or t bbm4 ) fall delay. figure 7 shows the switching cycle for the low side primary driver and associated synchronous driver and equation (1) shows the switching time components. at 500 khz and maximum duty t pd2 is typically 60 ns. t switch = 1/2t dt + t pd1 + t srloff + 1/2t dt - t pd2 - t bbm2 (1) the si9122e has an improved primary and secondary duty cycles with typical maximum secondary duty at 93.2 %. hence the dead-time is 6.8 % or 136 ns at 500 khz. half of the dead-time is 68 ns and during this time t pd2 plus t bbm2 has to occur before the next tr ansition point of the oscillator cycle. r bbm contributes 1.2 ns/k to t bbm2 ; with 33 k this amounts to 40 ns. if t bbm2 is set beyond the transition point, sr l will be forced high due to logic conditions and a reduction in the set t bbm2 will be determined by the half dead- time minus t pd2 and will be independent of the r bbm value as shown in figure 8. note: this applies to t bbm4 as well. to mitigate the decrease in set t bbm2 and t bbm4 , the following criteria must be met. the set t bbm2 plus its associated t pd2 must not exceed 3.4 % of the oscillator period. the typical t bbm2 and t bbm4 delays are provided in figure 9 to facilitate setting these delays for a given frequency with r bbm of 33 k . t bbm2 + t pd2 < 3.4 % of oscillator period (2) t bbm4 + t pd4 < 3.4 % of oscillator period (3) it is critical to avoid the condition where the sum of t bbm2 (set) and t pd2 is greater than 6.8 % of oscillator period whereby the correct sequence of logic signals cannot be guaranteed. figure 7. components of a low-side switching period dl sr v ep 1.2 v t pd1 bbm1 t p d2 bbm2 max ? deadtime ? deadtime transition point a b l figure 8. components of a low-side switching period with maximum duty and limited bbm2 figure 9. reduction in bbm2 and bbm4 si9122e bbm vs. f osc , v in = 50 v, v cc = 10 v, bst = 60 v, lx = 50 v, v ep = 0 v transition point dl sr 1.2 v t p d1 bbm1 t p d2 set bbm2 act u al bbm2 a b l 0 10 20 30 40 50 60 150 200 250 300 350 400 450 500 f osc (khz) delay (ns) bbm2 bbm4
www.vishay.com 12 document number: 73866 s-80112-rev. d, 21-jan-08 vishay siliconix si9122e typical characteristics f osc vs. r osc at v cc = 12 v v reg vs. temperature, v in = 48 v i ss vs. temperature 200 300 400 500 600 20 30 40 50 60 70 8 0 r osc (k ) ) z h k ( f c s o ) v ( v g e r temperat u re (c) 7.5 8 .0 8 .5 9.0 9.5 10.0 - 50 - 25 0 25 50 75 100 125 150 v i n det v ref tc = - 11 m v /c 15 17 19 21 23 25 - 50 - 25 0 25 50 75 100 125 temperat u re (c) v cc = 13 v v cc = 10 v v cc = 12 v ) a u ( i 1 s s v ref vs. temperature, v cc = 12 v sr l , sr h duty cycle vs. v ep v ss vs. temperature, v = 12 v 3.270 3.275 3.2 8 0 3.2 8 5 3.290 3.295 3.300 - 50 - 25 0 25 50 75 100 temperat u re (c) ) v ( v f e r 0 10 20 30 40 50 60 70 8 0 90 100 0.0 0.5 1.0 1.5 2.0 v ep ( v ) ) % ( e l c y c y t u d 3.6 v = v i n det v cc = 12 v 7.2 v 4. 8 v 7.90 7.95 8 .00 8 .05 8 .10 8 .15 8 .20 - 50 - 25 0 25 50 75 100 125 150 temperat u re (c) ) v ( v s s tc = + 1.25 m v /c v i n det v ref
document number: 73866 s-80112-rev. d, 21-jan-08 www.vishay.com 13 vishay siliconix si9122e typical characteristics i reg2 vs. temperature, v cc = 12 v dh, dl i source vs. v oh sr l , sr h i source vs. v oh 5 6 7 8 9 10 11 - 50 - 25 0 25 50 75 100 i 2 g e r ) a m ( temperat u re (c) 0 50 100 150 200 250 0 200 400 600 8 00 v oh (m v ) i e c r u o s ) a m ( v cc = 12 v 0 5 10 15 20 25 30 35 0 200 400 600 8 00 v oh (m v ) i e c r u o s ) a m ( v cc = 12 v i cc3 vs. temperature v cc = 12 v dh, dl i sink vs. v ol sr l , sr h i sink vs. v ol 7 8 9 10 11 12 13 - 50 - 25 0 25 50 75 100 temperat u re (c) i 3 c c ) a m ( 0 50 100 150 200 250 0 200 400 600 8 00 v cc = 12 v i k n i s ) a m ( v ol (m v ) 0 5 10 15 20 25 30 35 0 200 400 600 8 00 v ol (m v ) i k n i s ) a m ( v cc = 12 v
www.vishay.com 14 document number: 73866 s-80112-rev. d, 21-jan-08 vishay siliconix si9122e typical characteristics t bbm vs. r bbm , v ep = 0 v, v lx = 48 v, bst = 60 v, v indet = 4.8 v, f osc < 200 khz t bbm1, 2 vs. temperature, v ep = 0 v, f osc < 200 khz t bbm3, 4 vs. temperature, v ep = 0 v, f osc < 200 khz 20 30 40 50 60 70 8 0 90 100 25 30 35 40 45 t m b b ) s n ( r bbm (k ) v cc = 12 v t bbm1 t bbm2 t bbm3 t bbm4 30 40 50 60 70 8 0 - 50 - 25 0 25 50 75 100 125 v = 0 v r bbm = 33 k t , 1 m b b2 ) s n ( temperat u re (c) t bbm1, v cc = 13 v t bbm1, v cc = 10 v t bbm2, v cc = 13 v t bbm2, v cc = 10 v t bbm1, v cc = 12 v t bbm2, v cc = 12 v ep 30 35 40 45 50 55 60 65 70 - 50 - 25 0 25 50 75 100 125 t , 3 m b b 4 ) s n ( temperat u re (c) t bbm4, v cc = 13 v t bbm4, v cc = 12 v t bbm4, v cc = 10 v t bbm3, v cc = 13 v t bbm3, v cc = 10 v v ep = 0 v r bbm = 33 k t bbm3, v cc = 12 v f osc < 200 khz t bbm vs. r bbm , v ep = 1.65 v, v lx = 48 v, bst = 60 v, v indet = 4.8 v t bbm1, 2 vs. temperature, v ep = 1.65 v t bbm3, 4 vs. temperature, v ep = 1.65 v 15 25 35 45 55 65 25 30 35 40 45 t m b b ) s n ( r bbm (k ) v cc = 12 v t bbm1 t bbm2 t bbm3 t bbm4 30 35 40 45 50 55 60 - 50 - 25 0 25 50 75 100 125 t , 1 m b b 2 ) s n ( v ep = 1.65 v r bbm = 33 k t bbm1, v cc = 12 v t bbm1, v cc = 10 v t bbm2, v cc = 13 v t bbm2, v cc = 12 v t bbm2, v cc = 10 v t bbm1, v cc = 13 v temperat u re (c) 20 30 40 50 60 70 8 0 - 50 - 25 0 25 50 75 100 125 t , 3 m b b 4 ) s n ( t bbm4, v cc = 13 v t bbm4, v cc = 12 v t bbm4, v cc = 10 v t bbm3, v cc = 13 v t bbm3, v cc = 10 v v ep = 1.65 v r bbm = 33 k t bbm3, v cc = 12 v temperat u re (c)
document number: 73866 s-80112-rev. d, 21-jan-08 www.vishay.com 15 vishay siliconix si9122e typical characteristics t bbm1, 2 vs. v cc vs. v indet , f osc < 200 khz t bbm3, 4 vs. v cc vs. v indet , f osc < 200 khz i out vs. r load (v in = 72 v) 30 40 50 60 70 8 0 3.5 4.5 5.5 6.5 7.5 t , 1 m b b2 ) s n ( v i n det ( v ) v ep = 0 v t bbm1, v cc = 13 v t bbm1, v cc = 10 v t bbm2, v cc = 13 v t bbm2, v cc = 12 v t bbm2, v cc = 10 v t bbm1, v cc = 12 v 30 40 50 60 70 8 0 3.5 4.5 5.5 6.5 7.5 v i n det ( v ) t , 3 m b b4 ) s n ( v ep = 0 v t bbm4, v cc = 13 v t bbm4, v cc = 12 v t bbm4, v cc = 10 v t bbm3, v cc = 13 v t bbm3, v cc = 10 v t bbm3, v cc = 12 v lx = 4 8 v , bst = 60 v 0 10 20 30 40 50 60 0.0 0.2 0.4 0.6 0. 8 1.0 v . % e l c y c y t u d , i t u o r load () d % fre qu ency i out t u o v out 0 100 200 300 400 500 ) z h k ( y c n e u q e r f t bbm1, 2 vs. v cc vs. v indet t bbm3, 4 vs. v cc vs. v indet v rosc , f osc , and duty cycle vs. v cl_cont 35 40 45 50 55 3.5 4.5 5.5 6.5 7.5 t , 1 m b b2 ) s n ( v i n det ( v ) v ep = 1.65 v t bbm1, v cc = 13 v t bbm1, v cc = 12 v t bbm1, v cc = 10 v t bbm2, v cc = 13 v t bbm2, v cc = 10 v t bbm2, v cc = 12 v 30 35 40 45 50 55 60 65 3.5 4.5 5.5 6.5 7.5 v i n det ( v ) t , 3 m b b4 ) s n ( v ep = 1.65 v t bbm4, v cc = 13 v t bbm4, v cc = 12 v t bbm4, v cc = 10 v t bbm3, v cc = 12 v t bbm3, v cc = 10 v t bbm3, v cc = 13 v lx = 4 8 v , bst = 60 v 0 5 10 15 20 25 30 35 40 45 50 12345 v c ( v ) d % fre qu ency v r ) z h k ( y c n e u q e r f 0 200 300 400 500 d dl d sr 100 v c s o r f , ) v ( c s o hz k ( ) % ( e l c y c y t u d , ) l osc l_co n t
www.vishay.com 16 document number: 73866 s-80112-rev. d, 21-jan-08 vishay siliconix si9122e typical waveforms vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?73866 . figure 10. foldback mode, r l = 0.02 figure 12. v cc ramp-up figure 14. effective bbm - measured on secondary sr 10 v /di v i out 5 a /di v dl 10 v /di v cs2 50 m v /di v 2 s/di v l v i n 2 v /di v v cc 2 v /di v 2 ms/di v lx 20 v /di v sr 2 v /di v sr 2 v /di v 500 ns/di v h l figure 11. normal mode, r l = 0.1 figure 13. overload recovery figure 15. drive waveforms sr 10 v /di v dl 5 v /di v cs2 5 v /di v i out 5 a /di v 2 s/di v l v cl 2 v /di v v ep 2 v /di v i out 10 a/di v v out 2 v /di v 200 s/di v dh 5 v /di v sr 5 v /di v dl 5 v /di v sr 5 v /di v 500 ns/di v l h
1.00 seating plane 1.00 dia. d b e e/2 4x 0.20 c a ? bd 0.20 h a ? bd 2x n/2 tips 1.00 1.00 a n 123 see detail ?a? c l b b c e/2 x x = a and b lead sides top view h c aaa c a 1 a 2 a m c bbb a?b d 9 0.05 c b e d side view detail ?a? (scale: 30/1) (view rotated 90 c.w.) (14 ) h (14 ) 6 + + l ( ) 0.25 parting line end view e 1 package information vishay siliconix document number: 72818 28-jan-04 www.vishay.com 1 tssop: 20-lead (power ic only) millimeters dim min nom max a ? ? 1.10 a 1 0.05 ? 0.15 a 2 0.85 0.90 0.95 aaa 0.076 b 0.19 ? 0.30 b1 0.19 0.22 0.25 bbb 0.10 c 0.09 ? 0.20 c1 0.09 0.127 0.16 d 6.50 bsc e 6.40 bsc e 1 4.30 4.40 4.50 e 0.65 bsc l 0.50 0.60 0.70 n 20 p 4.2 p 1 3.0 0 ? 8 ecn: s-40082?rev. a, 02-feb-04 dwg: 5923
index area d/2 e/2 e d e/2 d/2 -a- -b- seating plane a3 a1 a c 0.08 c ccc // nx bottom view top view side view c aaa 2x c aaa 2x -c- index area d/2 e/2 nxb nxl 2.00 detail d d2/2 d2 e2/2 e2 nxb a bbb m b c 5 5 e/2 e terminal tip terminal tip e # identifier type a even terminal side odd terminal side chamber detail b package information vishay siliconix document number: 73182 15-oct-04 www.vishay.com 1 powerpak mlp65-18/20 (power ic only)
notes: 1. dimensioning and tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. all angels are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jedec publication 95 ssp-022. details of termi nal #1 identifier are optional, but must be located within the zone indicated. a dot can be marked on the top side by pin 1 to indicate orientation. 5. nd and ne refer to the number of terminals on the d and e side respectively. 6. depopulation is possible in a symmetrical fashion. 7. njr refers to non jedec registered. 8. dimension ?b? applies to metalized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. if the termin al has optional radius on the other end of the terminal, the dimension ?b? should not be measured in that radius area. 9. coplanarity applies to the exposed heat slug as well as the terminal. 10. the 45 chamfer dimension c? is located by pin 1 on the bottom side of the package. package information vishay siliconix www.vishay.com 2 document num ber: 73182 15-oct-04 powerpak mlp65-18/20 (power ic only) n = 18/20 pitch: 0.5 mm, body size: 6.00 x 5.00 millimeters* inches dim min nom max min nom max notes a 0.80 0.90 1.00 0.031 0.035 0.039 1, 2 a1 0.00 0.02 0.05 0.000 0.001 0.002 1, 2 a2 0.00 0.65 1.00 0.000 0.003 0.004 1, 2 a3 0.20 ref 0.008 ref aaa ? 0.15 ? ? 0.006 ? b 0.18 0.25 0.30 0.007 0.010 0.012 8 bbb ? 0.10 ? ? 0.004 ? c? ? 0.225 ? ? 0.009 ? 4, 10 ccc ? 0.10 ? ? 0.004 ? d 6.00 bsc 0.236 bsc 1, 2 d2 4.00 4.15 4.25 0.157 1.63 0.167 1, 2 e 5.00 bsc 0.197 bsc 1, 2 e2 3.00 3.15 3.25 0.118 0.124 0.128 1, 2 e ? 0.50 ? ? 0.020 ? l 0.45 0.55 0.65 0.018 0.022 0.026 1, 2 n 18, 20 18, 20 1, 2 nd(18) 9 9 1, 2 ne(18) 0 0 1, 2 nd(20) 10 10 1, 2 ne(20) 0 0 1, 2 * use millimeters as the primary measurement. ecn: s-41946?rev. a, 18-oct-04 dwg: 5939
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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